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1 ? caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004, 2010. all rights reserved. all other trademarks mentioned are the property of their respective owners. hip2100 100v/2a peak, low co st, high frequency half bridge driver the hip2100 is a high frequency, 100v half bridge n-channel power mosfet driver ic. the low-side and high-side gate drivers are independently controlled and matched to 8ns. this gives the user maximum flexibility in dead-time selection and driv er protocol. undervoltage protection on both the low-side and high-side supplies force the outputs low. an on-chip di ode eliminates the discrete diode required with other driver ics. a new level-shifter topology yields the low-power benefits of pulsed operation with the safety of dc operatio n. unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. features ? drives n-channel mosfet half bridge ? soic, epsoic, qfn and dfn package options ? soic, epsoic and dfn packages compliant with 100v conductor spacing guidelines of ipc-2221 ? pb-free product available (rohs compliant) ? bootstrap supply max voltage to 114vdc ? on-chip 1 bootstrap diode ? fast propagation times for multi-mhz circuits ? drives 1000pf load with rise and fall times typ. 10ns ? cmos input thresholds for improved noise immunity ? independent inputs for non-half bridge topologies ? no start-up problems ? outputs unaffected by supply glitches, hs ringing below ground, or hs slewing at high dv/dt ? low power consumption ? wide supply range ? supply undervoltage protection ?3 driver output resistance ? qfn/dfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package footprint, which improves pcb efficiency and has a thinner profile applications ? telecom half bridge power supplies ? avionics dc/dc converters ? two-switch forward converters ? active clamp forward converters ordering information part number (note 1) part marking temp. range (c) package pkg. dwg. # hip2100ib 2100 ib -40 to +125 8 ld soic m8.15 hip2100ibz (note 2) 2100 ibz -40 to +125 8 ld soic (pb-free) m8.15 hip2100eibz (note 2) 2100 eibz -40 to +125 8 ld epsoic (pb-free) m8.15c hip2100irz (note 2) hip 2100irz -40 to +125 16 ld 5x5 qfn (pb-free) l16.5x5 hip2100ir4z (note 2) 21 00ir4z -40 to +125 12 ld 4x4 dfn (pb-free) l12.4x4a notes: 1. add ?-t? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pa ckaged products employ special pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb- free requirements of ipc/jedec j std-020. data sheet april 2, 2010 fn4022.14
2 fn4022.14 application block diagram pinouts hip2100 (8 ld soic, epsoic) top view note: epad = exposed pad. hip2100ir4 (12 ld dfn) top view hip2100 (16 ld qfn) top view 5 6 8 7 4 3 2 1 v dd hb ho hs lo li hi v ss epad v dd nc nc hb ho lo v ss nc nc li hs 2 3 4 1 5 11 10 9 12 8 6 7hi epad 1 3 4 15 hb ho v dd lo 16 14 13 2 12 10 9 11 6 578 v ss li hs hi nc nc nc nc nc nc nc nc epad secondary circuit +100v control controller pwm li hi ho lo v dd hs hb +12v v ss hip2100 reference and isolation drive lo drive hi hip2100
3 fn4022.14 functional block diagram under voltage v dd hi li v ss driver driver hb ho hs lo level shift under voltage epad (epsoic, qfn and dfn packages only) *epad = exposed pad. the epad is electrical ly isolated from all other pins. for best thermal performance connect the epad to the pcb power ground plane. secondary hip2100 isolation pwm +48v +12v circuit figure 1. two-switch forward converter secondary circuit hip2100 isolation pwm +48v +12v figure 2. forward converter with an active clamp hip2100
4 fn4022.14 absolute maximum rati ngs thermal information supply voltage, v dd, v hb -v hs (notes 3, 4) . . . . . . . . -0.3v to 18v li and hi voltages (note 4) . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on lo (note 4) . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ho (note 4) . . . . . . . . . . . . . . . v hs -0.3v to v hb +0.3v voltage on hs (continuous) (note 4) . . . . . . . . . . . . . . -1v to 110v voltage on hb (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . . 100ma esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 (1kv) maximum recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . +9v to 14.0vdc voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs. . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . . v hs +8v to v hs +14.0v and v dd -1v to v dd +100v hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50v/ns thermal resistance (typical) ja (c/w) jc (c/w) soic (note 5) . . . . . . . . . . . . . . . . . . . 95 50 epsoic (note 6) . . . . . . . . . . . . . . . . . 40 3.0 qfn (note 6) . . . . . . . . . . . . . . . . . . . . 37 6.5 dfn (note 6) . . . . . . . . . . . . . . . . . . . . 40 3.0 max power dissipation at +25c in free air (soic, note 5) . . . . 1.3w max power dissipation at +25c in free air (epsoic, note 6) . . 3.1w max power dissipation at +25c in free air (qfn, note 6) . . . . . 3.3w storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature range. . . . . . . . . . . . . . . . . .-55c to +150c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. the hip2100 is capable of derated operation at supply voltages exceeding 14v. figure 16 shows the high-side voltage derating curve for this mode of operation. 4. all voltages referenced to v ss unless otherwise specified. 5. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 6. ja is measured in free air with the component mounted on a high ef fective thermal conductivity test board with ?direct attach? fe atures. jc, the ?case temp? is measured at the center of the exposed metal pad on the package underside. see tech brief tb379. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) supply currents v dd quiescent current i dd li = hi = 0v - 0.1 0.15 - 0.2 ma v dd operating current i ddo f = 500khz - 1.5 2.5 - 3 ma total hb quiescent current i hb li = hi = 0v - 0.1 0.15 - 0.2 ma total hb operating current i hbo f = 500khz - 1.5 2.5 - 3 ma hb to v ss current, quiescent i hbs v hs = v hb = 114v - 0.05 1 - 10 a hb to v ss current, operating i hbso f = 500khz - 0.7 - - - ma input pins low level input voltage threshold v il 45.4 - 3 - v high level input voltage threshold v ih -5.87 - 8 v input voltage hysteresis v ihys -0.4 - - - v input pulldown resistance r i - 200 - 100 500 k undervoltage protection v dd rising threshold v ddr 7 7.3 7.8 6.5 8 v v dd threshold hysteresis v ddh -0.5 - - - v hb rising threshold v hbr 6.5 6.9 7.5 6 8 v hb threshold hysteresis v hbh -0.4 - - - v hip2100
5 fn4022.14 boot strap diode low-current forward voltage v dl i vdd-hb = 100a - 0.45 0.55 - 0.7 v high-current forward voltage v dh i vdd-hb = 100ma - 0.7 0.8 - 1 v dynamic resistance r d i vdd-hb = 100ma - 0.8 1 - 1.5 lo gate driver low level output voltage v oll i lo = 100ma - 0.25 0.3 - 0.4 v high level output voltage v ohl i lo = -100ma, v ohl = v dd -v lo - 0.25 0.3 - 0.4 v peak pullup current i ohl v lo = 0v - 2 - - - a peak pulldown current i oll v lo = 12v - 2 - - - a ho gate driver low level output voltage v olh i ho = 100ma - 0.25 0.3 - 0.4 v high level output voltage v ohh i ho = -100ma, v ohh = v hb -v ho - 0.25 0.3 - 0.4 v peak pullup current i ohh v ho = 0v - 2 - - - a peak pulldown current i olh v ho = 12v - 2 - - - a electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) switching specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified. parameters symbol test conditions t j = +25c t j = -40c to + 125c units min typ max min (note 7) max (note 7) lower turn-off propagation dela y (li falling to lo falling) t lphl - 20 35 - 45 ns upper turn-off propagation delay (hi falling to ho falling) t hphl - 20 35 - 45 ns lower turn-on propagation delay (li rising to lo rising) t lplh - 20 35 - 45 ns upper turn-on propagation dela y (hi rising to ho rising) t hplh - 20 35 - 45 ns delay matching: lower turn-on and upper turn-off t mon - 2 8 - 10 ns delay matching: lower turn-off and upper turn-on t moff - 2 8 - 10 ns either output rise/fall time t rc , t fc c l = 1000pf - 10 - - - ns either output rise/fall time (3v to 9v) t r , t f c l = 0.1f - 0.5 0.6 - 0.8 s either output rise time driving dmos t rd c l = irfr120 - 20 - - - ns either output fall time driving dmos t fd c l = irfr120 - 10 - - - ns minimum input pulse width that changes the output t pw - - - - 50 ns bootstrap diode turn-on or turn-off time t bs -10 - - - ns note: 7. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established by characterization and are not production tested. hip2100
6 fn4022.14 timing diagrams pin descriptions symbol description v dd positive supply to lower gate drivers. de-couple this pin to v ss . bootstrap diode connected to hb. hb high-side bootstrap supply. external bootst rap capacitor is required. connect positive side of bootstrap capacitor to this pi n. bootstrap diode is on-chip. ho high-side output. connect to gate of high-side power mosfet. hs high-side source connection. connect to s ource of high-side power mosfet. connect negative side of bootstrap capacitor to this pin. hi high-side input. li low-side input. v ss chip negative supply, generally will be ground. lo low-side output. connect to gate of low-side power mosfet. epad exposed pad. connect to ground or float. the epad is electrically isolat ed from all other pins. figure 3. figure 4. t hplh , t lplh t hphl , t lphl hi , li ho , lo t mon t moff li hi lo ho typical performance curves figure 5. operating current vs frequency figure 6. hb to v ss operating current vs frequency t = +125c t = +25c t = -40c t = +150c 10k 100k 1m 10 1 0.1 0.01 frequency (hz) i ddo , i hbo (ma) t = -40c t = +125c t = +25c t = +150c 10 1 0.1 0.01 i hbso (ma) 10k 100k 1m frequency (hz) hip2100
7 fn4022.14 figure 7. high level output voltage vs temperature figure 8. low level output voltage vs temperature figure 9. undervoltage lockout threshold vs temperature figure 10. undervoltage lockout hysteresis vs temperature figure 11. propagation delays vs temperature figure 12. peak pullup current vs output voltage typical performance curves (continued) temperature (c) v ohl , v ohh (mv) 500 400 300 200 100 -50 0 50 100 150 v hb = v dd = 9v v hb = v dd = 12v v hb = v dd = 14v temperature (c) v oll , v olh (mv) 500 400 300 200 100 -50 0 50 100 150 v hb = v dd = 9v v hb = v dd = 12v v hb = v dd = 14v temperature (c) -50 0 50 100 150 7.6 7.4 7.2 7.0 6.8 6.6 v ddr v hbr v hbr , v ddr (v) temperature (c) -50 0 50 100 150 0.54 0.50 0.46 0.42 0.38 0.30 v ddh v hbh v hbh , v ddh (mv) 0.34 t hphl t hplh t lphl t lplh temperature (c) -50 0 50 100 150 30 25 20 15 t lplh , t lphl , t hplh , t hphl (ns) 6 2.0 i ho , i lo (a) 12 10 8 4 2 0 2.5 1.5 1.0 0.5 0 v ho , v lo (v) hip2100
8 fn4022.14 figure 13. peak pulldown current vs output voltage figure 14. bootstrap diode i-v characteristics figure 15. quiescent current vs voltage figure 16. v hs voltage vs v dd voltage typical performance curves (continued) 6 2.0 i lo , i ho (a) 12 10 8 4 2 0 2.5 1.5 1.0 0.5 0 v lo , v ho (v) 0.8 1.000 0.100 0.010 0.001 110 -4 110 -5 110-6 0.7 0.6 0.5 0.4 0.3 forward voltage (v) forward current (a) v dd , v hb (v) 051015 60 50 40 0 i dd , i hb (a) 30 20 10 i dd vs v dd i hb vs v hb 120 100 80 60 40 20 0 14 15 16 12 v hs to v ss voltage (v) v dd to v ss voltage (v) hip2100
9 fn4022.14 hip2100 dual flat no-lead plastic package (dfn) micro lead frame plastic package (mlfp) top view index d1/2 d1 d/2 d e1/2 e/2 e1 e a 2x 0.15 b c a n bottom view seating plane 5 6 2 3 1 0.10 nx b a1 c 2x c 0.15 0.15 2x b 0 a1 a c c b 2x a c 0.15 a2 a3 area // side view 0.08 c 4x 9 l 5 nx b 4x p n e b 0.10 c a d2 e2 1 (nd-1)xe ref. 3 2 m 7 8 8 7 6 area index n-1 d2/2 nx k 5 e2/2 e for even terminal/side l c terminal tip c c l12.4x4a 12 lead dual flat no-lead plastic package symbol millimeters notes min nominal max a - 0.85 0.90 - a1 0.00 0.01 0.05 - a2 - 0.65 0.70 - a3 0.20 ref - b 0.18 0.23 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc - d2 2.65 2.80 2.95 7, 8 e 4.00 bsc - e1 3.75 bsc - e2 1.43 1.58 1.73 7, 8 e 0.50 bsc - k 0.635 - - - l 0.30 0.40 0.50 8 n122 nd 6 3 p 0.24 0.42 0.60 - --12- rev. 0 8/03 notes: 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. n is the number of terminals. 3. nd refer to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 i dentifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are for the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see inters il technical brief tb389. 9. compliant to jedec mo-229-vggd-2 issue c except for the l dimension .
10 fn4022.14 hip2100 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.5x5 16 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhb issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.28 0.33 0.40 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.55 2.70 2.85 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.55 2.70 2.85 7, 8 e 0.80 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 4 3 p- -0.609 --129 rev. 2 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
11 fn4022.14 hip2100 small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 8 0 8 - rev. 1 6/05
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn4022.14 hip2100 small outline exposed pad plastic packages (epsoic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m p1 123 p bottom view n top view side view m8.15c 8 lead narrow body small outline exposed pad plastic package symbol inches millimeters notes min max min max a 0.056 0.066 1.43 1.68 - a1 0.001 0.005 0.03 0.13 - b 0.0138 0.0192 0.35 0.49 9 c 0.0075 0.0098 0.19 0.25 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.811 3.99 4 e 0.050 bsc 1.27 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n8 87 0 8 0 8 - p - 0.126 - 3.200 11 p1 - 0.099 - 2.514 11 rev. 1 6/05 notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. 11. dimensions ?p? and ?p1? are t hermal and/or electrical enhanced variations. values shown are maximum size of exposed pad within lead count and body size.

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